Design of an Analog CMOS Based Interval Type-2 Fuzzy Logic Controller Chip

We propose the design of an analog Interval Type-2 (IT2) fuzzy logic controller chip that is based on the realization approach of averaging of two Type-1 Fuzzy Logic Systems (T1 FLSs). The fuzzifier is realized using transconductance mode membership function generator circuits. The membership functions are made tunable by setting some reference voltages on the IC pins. The inference is realized using current mode MIN circuits. The consequents are also tunable by providing five reference current sources on chip. Defuzzification of both the T1 FLSs is based on weighted average method realized through scalar and multiplier-divider circuits. An analog current-mode averager circuit is used for obtaining the defuzzified output of the IT2 fuzzy logic controller chip. The chip is designed for two inputs, one output and nine tunable fuzzy rules and is realized in 0.18 μm technology. Cadence Virtuoso Schematic/Layout Editor has been used for the chip design and the performances of all the circuits are confirmed through the simulations carried out using Cadence Spectre tool. The proposed architecture has an operation speed of 20 MFLIPS and a power consumption of 20mW. The whole chip occupies an area of 0.32 mm 2 . As compared to the previous designs, the proposed design has achieved a considerable high speed along with a significant reduction in power and area.